The present invention relates generally to integrated circuits, and more particularly, to an adaptive pin allocation circuit for integrated circuits.
Many integrated circuits (ICs) such as processors and Systems on a Chip (SoC) are connected to external devices such as random access memory (RAM), wireless communication systems, a camera, and the like by way of input/output (IO) pins. The IO pins are connected to corresponding IO pads of the IC or SoC. Herein SoC will be used to connote both processors and SoCs. The SoC includes multiple device controllers corresponding to the external or off-chip devices that facilitate communication between the off-chip devices and a processor of the SoC.
An off-chip device may transmit to and receive data from a corresponding device controller using multiple IO pads. However, since the SOC will have a limited number of IO pins, it is more efficient to have some devices share IO pins, such that multiple off-chip devices communicate with the SOC using the same IO pins. When off-chip devices share an IO pin, the SoC uses a pin multiplexing circuit (hereinafter a “pin-mux circuit”) to facilitate the sharing of the pad.
A conventional pin-mux circuit includes a multiplexer, a demultiplexer, and a register. The off-chip devices are connected to the SoC with multiple pins and their corresponding IO pads. The SoC includes multiple pin-mux circuits that correspond to the multiple IO pads. Each pin-mux circuit includes a corresponding register, which stores a MUX select word corresponding to one of the IO pads. A multiplexer is connected to the device controllers and receives data bits from the controllers. The multiplexer also receives the MUX select word as a select signal from the register. The multiplexer outputs a data bit corresponding to a device and a device controller based on the MUX select word. The device corresponding to the device controller then receives the data bit by way of the IO pad.
A demultiplexer is connected to the multiple devices by way of the IO pad and receives data bits from the multiple devices. The demultiplexer also receives the MUX select word as a select signal from the register. The demultiplexer outputs a data bit from a device to a corresponding device controller based on the MUX select word. The SoC includes multiple such pin-mux circuits corresponding to the multiple IO pads for communicating with the multiple devices, and each of the pin-mux circuits includes a corresponding register for storing a corresponding MUX select word.
Typically, the MUX select word is written to the register using a C language command. For example, if the SoC includes two hundred IO pads, then two hundred C language commands are written to the corresponding two hundred registers to configure the two hundred pin-mux control circuits. The large number of registers results in a large area overhead, and the large number of write commands wastes processing time.
U.S. Pat. No. 8,813,015 discloses a SoC having multiple IO pads, where the SoC is connected to a memory device by way of the IO pads. An allocation register is used to allocate IO pads to input bits. The allocation register receives the input bits from various on-chip and off-chip devices, and outputs the input bits to the memory device by way of the IO pads based on multiple control signals. Multiple registers are needed to store the multiple control signals. The allocation register includes multiple multiplexers corresponding to the multiple IO pads. The multiplexers receive the control signals from the registers.
In one instance, the SoC includes N IO pads (P1-Pn). Hence, the allocation register includes N multiplexers (M1-Mn) corresponding to the N IO pads. Each multiplexer receives N input bits (I1-In), and the corresponding control signal (C1-Cn). For example, a multiplexer M1 outputs one input bit of the N input bits based on its corresponding control signal C1. The corresponding IO pad P1 receives the control signal C1. Since there are N control signals, the SoC includes N registers. Multiple registers required for allocation of the N input bits to the N IO pads increases the area of the SoC. Further, the SoC requires N commands to allocate the N input bits to the N IO pads, which uses excessive processor time to configure the registers.
It would be advantageous to have an SoC with pin-mux circuits that use fewer registers and requires fewer commands to configure the registers.